基于SRAM型FPGA的多源自主重构方法

doi:10.12305/j.issn.1001-506X.2022.04.04

Abstract

Abstract:

The space radiation environment causes the single event upset(SEU) problem of static random-access memory (SRAM) type field programmable gate array (FPGA), and its severity may affect the normal operation of the system. This architecture is a multi-source reconstruction method based on Xilinx Virtex series FPGA, which can independently identify various Xilinx Virtex series FPGA, and use different program memory sources to refresh and reconstruct SRAM type FPGA flexibly. Moreover, it can also program SRAM FPGA to solve some on-orbit problems, effectively reduce the impact of SRAM FPGA on on-orbit single-particle problems, and successfully achieve the reliability scheme of on-orbit timing refresh+multi-source+autonomous mode anti-single particle reinforcement. The design is applied to the space remote sensing infrared camera, and the on-orbit operation shows that the design can effectively reduce the number of single-particle flips, and satisfy the image performance of the system through on-orbit autonomous reconstruction.

Key words: autonomous, multi-source, reconfiguration, refresh

CLC Number:

Lufang LI, Shuangxi ZHOU, Huage HEI, Qichao YU, Changqing LIN, Shengli SUN. Multi-source autonomous reconstruction method based on SRAM FPGA[J]. Systems Engineering and Electronics, 2022, 44(4): 1093-1102.

Figures/Tables 13

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References 31

1	PHILIPPE A , GREG A . Assessing and mitigating radiation effects in xilinx FPGAs[M]. California: Propulsion Laboratory California Institute of Technology, 2008.
2	RAO Y, CHEN W, CAO Z G. A sequential sensing data transmission and fusion approach for large scale cognitive radios[C]//Proc. of the IEEE International Conference on Communications, 2010.
3	XING K F , YANG J , WANG Y K , et al. The research of anti-radiation technology on Xilinx SRAM-based FPGA[J]. Journal of Astronautics, 2007, 28 (1): 123- 129.
4	ITURBE X, AZKARATE M, MARTINEZ I, et al. A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs[C]//Proc. of the 19th International Conference on Field Programmable Logic and Applications, 2009.
5	马寅, 安军社, 王连国, 等. 基于Scrubbing的空间SRAM型FPGA抗单粒子翻转系统设计[J]. 空间科学学报, 2012, 32 (2): 270- 276.
	MA Y , AN J S , WANG L G , et al. Design of space SRAM FPGA anti-single particle flip system based on scrubbing[J]. Chinese Journal of Space Science, 2012, 32 (2): 270- 276.
6	复旦微电子. 航天应用SEU加固推荐方案, JFM4VSX55RT[R]. 上海: 复旦微电子, 2017: 4-16.
	Fudan Microelectronics. Recommended SEU reinforcement scheme for aerospace applications, JFM4VSX55RT[R]. Shanghai: Fudan Microelectronics, 2017: 4-16.
7	PRAVEEN K S , JEREMY R , SRINIVAS K . Selective triple modular redundancy (STMR) based single-event upset (SEU) tolerant synthesis for FPGAs[J]. IEEE Trans.on Nuclear Science, 2004, 51 (5): 2957- 2969. doi: 10.1109/TNS.2004.834955
8	STERPONE L , VIOLANTE M , JEREMY R , et al. Analysis of the robustness of the TMR architecture in SRAM-based FPGAs[J]. IEEE Trans.on Nuclear Science, 2005, 52 (5): 1545- 1549. doi: 10.1109/TNS.2005.856543
9	UG156. Xilinx TMR tool user guide[S]. SAN Jose: Xilinx, 2006.
10	KASTENSMIDT F L , CARRO L , REIS R . Fault-tolerance techniques for SRAM-based FPGAs[M]. New York: Springer, 2006.
11	ZOU W X, ZHANG W S, ZHOU Z, et al. Chain-based or rule cooperative spectrum sensing scheme in cognitive sensing networks[C]//Proc. of the International Symposium on Communications and Information Technologies, 2010: 1191-1195.
12	FULLER E, CAFFREY M, SALAZAR A, et al. Radiation testing update, SEU mitigation, and availability analysis of the Virtex FPGA for space reconfigurable computing[C]//Proc. of the 4th Annual Conference on Military and Aerospace Programmable Logic Devices, 2000.
13	GEORGE G, REZGUI S, SWIFT G, et al. Initial single-event effects testing and mitigation in the Xilinx Virtex Ⅱ-Pro FPGA[C]//Proc. of the Military and Aerospace Programmable Logic Devices International Conference, 2005.
14	CARL C, EARL F, JOE F, et al. Proton testing of SEU mitigation methods for the Virtex FPGA[C]//Proc. of the IEEE Microelectronics Reliability and Qualification Workshop, 2001.
15	张宇宁, 张小林, 杨根庆, 等. 商用FPGA器件的单粒子效应模拟实验研究[J]. 宇航学报, 2009, 30 (5): 2025- 2030. doi: 10.3873/j.issn.1000-1328.2009.05.047
	ZHANG Y N , ZHANG X L , YANG G Q , et al. Experimental study on single particle effect simulation of commercial FPGA devices[J]. Journal of Astronautics, 2009, 30 (5): 2025- 2030. doi: 10.3873/j.issn.1000-1328.2009.05.047
16	侯建文, 张爱兵, 郑香脂, 等. FPGA单粒子翻转事件在轨探测研究[J]. 宇航学报, 2014, 35 (4): 454- 458. doi: 10.3873/j.issn.1000-1328.2014.04.012
	HOU J W , ZHANG A B , ZHENG X Z , et al. On-orbit detection of FPGA single particle flip events[J]. Journal of Astronautics, 2014, 35 (4): 454- 458. doi: 10.3873/j.issn.1000-1328.2014.04.012
17	邱金娟, 徐宏杰, 潘雄, 等. SRAM型FPGA单粒子翻转测试及加固技术研究[J]. 电光与控制, 2011, 18 (8): 84- 88. doi: 10.3969/j.issn.1671-637X.2011.08.020
	QIU J J , XU H J , PAN X , et al. Research on single particle flip test and reinforcement technology of SRAM FPGA[J]. Electrooptics and Control, 2011, 18 (8): 84- 88. doi: 10.3969/j.issn.1671-637X.2011.08.020
18	宋凝芳, 朱明达, 潘雄. SRAM型FPGA单粒子效应试验研究[J]. 宇航学报, 2012, 33 (6): 836- 842. doi: 10.3873/j.issn.1000-1328.2012.06.022
	SONG N F , ZHU M D , PAN X . Experimental study on single particle effect of SRAM FPGA[J]. Journal of Astronautics, 2012, 33 (6): 836- 842. doi: 10.3873/j.issn.1000-1328.2012.06.022
19	胡洪凯, 施蕾, 董暘暘, 等. SRAM型FPGA空间应用的抗单粒子翻转设计[J]. 航天器环境工程, 2014, 31 (5): 510- 515. doi: 10.3969/j.issn.1673-1379.2014.05.010
	HU H K , SHI L , DONG Y Y , et al. Anti-single particle flip design for SRAM FPGA space applications[J]. Spacecraft Environment Engineering, 2014, 31 (5): 510- 515. doi: 10.3969/j.issn.1673-1379.2014.05.010
20	郑晓云, 陶淑苹, 冯汝鹏, 等. SRAM型FPGA抗单粒子翻转技术研究[J]. 电子测量技术, 2015, 38 (1): 59- 63. doi: 10.3969/j.issn.1002-7300.2015.01.014
	ZHENG X Y , TAO S P , FENG R P , et al. Research on anti-single particle flip technology of SRAM FPGA[J]. Electronic Measurement Technology, 2015, 38 (1): 59- 63. doi: 10.3969/j.issn.1002-7300.2015.01.014
21	高鹏, 庞宗强, 周同. Virtex FPGA抗单粒子翻转技术[J]. 综合电子信息技术, 2014, 40 (4): 73- 76.
	GAO P , PANG Z Q , ZHOU T . Virtex FPGA anti-single particle flip technology[J]. Integrated Electronic Information Technology, 2014, 40 (4): 73- 76.
22	南希, 龚龙庆, 田卫平, 等. 基于FPGA的动态可重构系统设计与实现[J]. 现代电子技术, 2009, 293 (6): 4- 11. doi: 10.3969/j.issn.1004-373X.2009.06.002
	NAN X , GONG L Q , TIAN W P , et al. Design and implementation of dynamic reconfigurable system based on FPGA[J]. Modern Electrical Technology, 2009, 293 (6): 4- 11. doi: 10.3969/j.issn.1004-373X.2009.06.002
23	BOLCHINI C, MIELE A, SANTAGO M D. TMR and partial dynamic reconfiguration to mitigate SEU faults in FPGAs[C]//Proc. of the IEEE 22nd International Symposium on Defect and Fault-Tolerance in VLSI Systems, 2007: 87-95.
24	CARMICHAEL C, FULLER E, BLAIN P, et al. SEU mitigation techniques for Vitex FPGAs in space application[C]//Proc. of the 2nd Military and Aerospace Programmable Logic Devices, 1999: 24-34.
25	YUI C C, SWIFT G M, CARMICHAEL C, et al. SEU mitigation testing of Xilinx Virtex Ⅱ FPGAs[C]//Proc. of the IEEE Nuclear and Space Radiation Effects Conference, 2003: 92- 97.
26	XAPP779. Correcting single-event upsets in Virtex-Ⅱ platform FPGA configuration memory[S]. SAN Jose: Xilinx, 2007.
27	XAPP1088. Correcting single-event upsets in Virtex-4 FPGA configuration memory[S]. SAN Jose: Xilinx, 2009.
28	UG002. Virtex-Ⅱ platform FPGA user guide[S]. SAN Jose: Xilinx, 2004.
29	UG071. Virtex-4 FPGA configuration user guide[S]. SAN Jose: Xilinx, 2009.
30	UG191. Virtex-5 FPGA configuration user guide[S]. SAN Jose: Xilinx, 2020.
31	UG470.7. Series FPGA configuration user guide[S]. SAN Jose: Xilinx, 2018.

参数性能	文献[5]	文献[19]	文献[20]	文献[21]	文献[22]	刷新芯片	本文
关键逻辑TMR	/	√	/	√	/	/	√
部分重配置	√	√	√	√	√	√	√
重配置	/	√	/	/	√	√	√
回读寄存器	/	/	/	/	/	√	√
支持多种FPGA	/	/	/	/	/	支持部分型号	支持可重构全部型号
支持外部存储器	/	/	/	/	/	支持部分型号	支持可上注全部型号
自主程序重构调整参数和预设程序上注	/	/	/	/	/	仅支持程序上注	√
优点	设计相对简单	设计相对简单	设计相对简单	设计相对简单	设计相对简单	不需要代码实现, 芯片预留用户接口	系统设计灵活性高, 兼容FPGA型号以及外部存储器型号较多
缺点	需要代码实现, 设计灵活性较低, 纠错能力最弱	需要代码实现, 设计灵活性较低, 纠错能力较弱	需要代码实现, 设计灵活性较低, 纠错能力最弱	需要代码实现, 设计灵活性较低, 纠错能力较弱	需要代码实现, 设计灵活性较低, 纠错能力较弱	更改灵活性差, 兼容FPGA型号以及外部存储器型号有限	需要代码实现

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Multi-source autonomous reconstruction method based on SRAM FPGA

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References 31

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