基于元件降额设计的温度步进强化试验剖面设计

doi:10.12305/j.issn.1001-506X.2023.12.38

系统工程与电子技术 ›› 2023, Vol. 45 ›› Issue (12): 4073-4083.doi: 10.12305/j.issn.1001-506X.2023.12.38

• 可靠性 • 上一篇

基于元件降额设计的温度步进强化试验剖面设计

薛小锋¹, 徐光铎¹^,*, 冯蕴雯¹, 刘佳奇¹, 高涛², 郭世玺², 张薇³

1. 西北工业大学航空学院, 陕西西安 710072
2. 西安机电信息技术研究所, 陕西西安 710065
3. 西安昆仑工业(集团)有限责任公司, 陕西西安 710043

收稿日期:2023-03-20 出版日期:2023-11-25 发布日期:2023-12-05
通讯作者: 徐光铎
作者简介:薛小锋(1982—), 男, 副研究员, 博士, 主要研究方向为可靠性工程、武器装备试验技术
徐光铎(1999—), 男, 硕士研究生, 主要研究方向为武器装备试验技术
冯蕴雯(1968—), 女, 教授, 博士, 主要研究方向为可靠性维修工程、飞行器设计
刘佳奇(1993—), 男, 博士研究生, 主要研究方向为复杂系统可靠性、运行支持与健康管理
高涛(1987—), 男, 工程师, 博士, 主要研究方向为武器装备试验技术
郭世玺(1996—), 女, 助理工程师, 硕士, 主要研究方向为武器装备试验技术
张薇(1976—), 女, 高级工程师, 本科, 主要研究方向为武器装备技术设计
基金资助:
国家自然科学基金(51875465)

Design of temperature stepping enhancement test profile based on component derating design

Xiaofeng XUE¹, Guangduo XU¹^,*, Yunwen FENG¹, Jiaqi LIU¹, Tao GAO², Shixi GUO², Wei ZHANG³

1. School of Aeronautics, Northwestern Polytechnical University, Xi'an 710072, China
2. Xi'an Institute of Mechanical and Electrical Information Technology, Xi'an 710065, China
3. Xi'an Kunlun Industry (Group) Company Limited, Xi'an 710043, China

Received:2023-03-20 Online:2023-11-25 Published:2023-12-05
Contact: Guangduo XU

摘要/Abstract

摘要：

针对目前强化试验剖面效率低、成本高的问题, 提出了某型弹类电子产品温度强化试验剖面设计框架。结合产品可靠性框图对试验对象进行失效逻辑分析, 基于元器件降额的步长设计方法(step design method based on component derating, CD-SDM)优化步长、缩短试验时间, 采用基于有限元仿真的确定性分析方法获得工作极限和破坏极限估值, 降低步长划分时极限间工作裕度的影响, 实现步长、试验时间和其他要素的优化。以某型弹类电子产品高温步进为例验证所提方法, 结果表明获得的温度强化试验剖面较传统方法在试验时间上最少可缩短13.33%左右, 与传统方法相比减少了1/4的检测次数, 优化了目前可靠性强化试验剖面设计对弹类电子产品试验效率低、成本高的问题。

关键词: 可靠性强化试验, 降额设计, 试验剖面, 热仿真, 弹类电子产品

Abstract:

Aiming at the problems of low efficiency and high cost of the enhanced test profile, a design framework for the temperature enhancement test profile of a certain missile electronics is proposed. Combined with the product reliability block diagram, the failure logic analysis of the test object is carried out. The step design method based on component derating (CD-SDM) optimizes the step size and shortens the test time, and the deterministic analysis method based on finite element simulation is used to obtain the working limit and the failure limit estimation, which reduce the influence of the working margin between the limits when the step size is divided and realize the optimization of step size, test time and other elements. Taking a high-temperature stepping test of a certain missile electronics as an example to verify the proposed method, the experimental results show that the temperature strengthening test profile obtained can be shortened by at least 13.33% in test time compared with the traditional methods, and the number of detection times is reduced by 1/4 compared with the traditional methods, which optimizes the problem of low efficiency and high cost of the current reliability enhancement test profile design for missile electronics.

Key words: reliability enhancement testing, derating design, test profile, thermal simulation, missile electronics

中图分类号:

TJ06

薛小锋, 徐光铎, 冯蕴雯, 刘佳奇, 高涛, 郭世玺, 张薇. 基于元件降额设计的温度步进强化试验剖面设计[J]. 系统工程与电子技术, 2023, 45(12): 4073-4083.

Xiaofeng XUE, Guangduo XU, Yunwen FENG, Jiaqi LIU, Tao GAO, Shixi GUO, Wei ZHANG. Design of temperature stepping enhancement test profile based on component derating design[J]. Systems Engineering and Electronics, 2023, 45(12): 4073-4083.

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应用范围	降额等级
应用范围	最高	最低
航天器与运载火箭	Ⅰ	Ⅰ
战略导弹	Ⅰ	Ⅱ
战术导弹系统	Ⅰ	Ⅲ
飞机与舰船系统	Ⅰ	Ⅲ
通信电子系统	Ⅰ	Ⅲ
武器与车辆系统	Ⅰ	Ⅲ
地面保障系统	Ⅱ	Ⅲ

序号	元器件名称	功耗
1	放大器芯片	0.006 5
2	A/D转换器	0.005 2
3	FPGA芯片	0.749 0
4	升压芯片	0.015 0
5	降压芯片	0.002 0

序号	器件类型	降额后最高允许结温	降额后最低允许结温	最高允许结温	最低允许结温
1	放大器芯片	-45	85	-65	105
2	A/D转换器	-45	85	-65	105
3	FPGA芯片	-55	85	-75	105
4	升压芯片	-45	85	-65	105
5	降压芯片	-45	85	-65	105

材料名称	密度/(g/cm³)	导热系数/(W/m·K)	比热容/(J/kg·℃)
聚四氟乙烯	2.14	0.24	1 050
PCB板	1.80	38(水平), 0.35(竖直)	1 465
硅	2.34	1.13	700
铝合金	2.83	180	860
陶瓷	5.60	1.22	390
铜	8.90	401	386

型号	工作范围/℃	升降温变速率/(℃/min)	精度/℃
SUS00C-150-ESS	-70~+180	≥15(-55~+80)	±2

基于元件降额设计的温度步进强化试验剖面设计

Design of temperature stepping enhancement test profile based on component derating design

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参考文献 34

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Metrics

本文评价

型号	测量范围/℃	精度/℃	响应时间/s
WZP-PT100	-70~+500	±(0.3=0.000 5\|K\|) (K为绝对温度)	T_0.5=3.0 T_0.9=10.0

型号	测量通道/路	采样周期/s	数据内存/万条	预热时间/min
HSTL-PLR110	4	1	90(128 Mb)	30

温度测试点	试验数据		仿真数据
温度测试点	平衡温度/℃	平衡时长/min	平衡温度/℃	平衡时长/min
1	-51.4	108	-48.5	88
2	-50.3	158	-49.3	148
3	-50.3	158	-49.3	148
4	-51.3	158	-49.5	148

序号	元器件	结温	降额后允许结温	最高允许结温	差值
1	放大器	25.17	85	105	59.83
2	AD转换器	25.07	105	135	79.93
3	FPGA芯片	33.34	85	105	51.66
4	升压芯片	25.05	85	105	59.95
5	降压芯片	25.03	85	105	59.97

序号	温度量级/℃	热稳定时间/min
1	32.0	116.00
2	42.0	116.00
3	52.0	116.00
4	57.0	86.33
5	62.0	86.33
6	67.0	86.33
7	72.0	86.33
8	77.0	86.33
9	82.0	86.33
10	87.0	86.33
11	92.0	86.33
12	97.0	86.33

序号	划分方法	步长/℃	总步进时间/min
1	传统方法(变步长)	10;5	12T_t+1 124.97
2	均分法(恒定步长)	7	10T_t+1 080.00
3	CD-SDM	9;7	9T_t+936.00

序号	试验温度/℃	步长/℃	检测结果
1	31	无	正常
2	40	9	正常
3	49	9	正常
4	58	9	正常
5	67	9	正常
6	76	9	异常
7	67	无	正常
8	72	5	正常
9	75	3	异常

序号	温度量级/℃	热稳定时间/min
1	29.5	108.00
2	37.0	108.00
3	44.5	108.00
4	52.0	108.00
5	59.5	108.00
6	67.0	108.00
7	74.5	108.00
8	82.0	108.00
9	89.5	108.00
10	97.0	108.00

序号	温度量级/℃	热稳定时间/min
1	31	108.00
2	40	108.00
3	49	108.00
4	58	108.00
5	67	108.00
6	76	108.00
7	83	96.00
8	90	96.00
9	97	96.00