一种伯努利粒子滤波器的FPGA实现

doi:10.12305/j.issn.1001-506X.2025.02.07

Abstract

Abstract:

Aiming at the high-speed and efficient computing problem of Bernoulli particle filters in embedded application environments, taking the Bernoulli particle filters for joint detection and estimation of radar weak targets as an example, a function modularized and particle size scalable field programmable gate array (FPGA) implementation architecture is proposed. The computing speed of filtering calculation is further improved through approaches as particle state pipelining, layered accumulation and sum, and parallel resampling, etc. Xilinx ZC706 evaluation board on-board testing experiments have demonstrated the good scalability and excellent acceleration ratio of the proposed architecture. When the number of particles is 1 024, the acceleration ratio is about 10⁴ orders of magnitude compared to the Intel Core i3-4130 CPU computing environment. The results have important reference value for the application of Bernoulli particle filtering technology in radar, robotics, and navigation guidance fields.

Key words: Bernoulli particle filter, field programmable gate array (FPGA), real-time signal processing, pipelining parallelization, resample, joint detection and estimation

CLC Number:

TN953

Hongfei LIAN, Dongsheng LI, Yanwen JIANG, Hongqi FAN, Huaitie XIAO, Guoyan WANG. FPGA implementation of a Bernoulli particle filter[J]. Systems Engineering and Electronics, 2025, 47(2): 398-405.

Figures/Tables 13

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References 30

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参数名称	取值
存活粒子个数N	512
新生粒子个数B	512
输入序列长度L/点	250
参数名称	取值
采样时间/ms	5
输入信号信噪比/dB	4
系统时钟频率/MHz	200

计算单元名称	时间
更新单元	45.30
重采样单元	24.96
状态提取单元	21.71
随机数产生单元	5.16
存活粒子预测单元	4.54
粒子新生单元	5.54

资源类型	消耗量/个	占比/%
FF	28 598	6.5
LUT	45 632	20.8
BRAM	84	7.7
DSP Slices	132	14.6

计算环境	均值	误差
FPGA	-500.81	0.81
CPU	-501.25	1.25

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FPGA implementation of a Bernoulli particle filter

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