基于ASIC和FPGA的可扩展红外信息获取架构设计

doi:10.12305/j.issn.1001-506X.2025.04.04

Abstract

Abstract:

With the continuous development of remote sensing technology, ultra-large scale infrared detector components are gradually applied in the field of earth observation, which brings new requirements for information acquisition technology: simultaneously processing of hundreds of tap signals acquisition, conditioning, sampling, quantization and signal preprocessing with each tap readout frequency of up to 10 MHz or more. Aiming at the application scenario of a new large-scale infrared detector, a smart and highly integrated large-scale infrared information acquisition electronics architecture based on field-programmable gate array (FPGA) and application specific integrated circuit (ASIC) is designed. With an expandable modular design, a single information acquisition module can collect 64-channel signals. When the analog to digital (AD) sampling rate of each channel is 12 mega samples per second (MSPS), the maximum data rate of the single channel module is not less than 12 Gbps, which realizes the integration of information acquisition, processing and transmission of ultra-large scale infrared detector, solves the problem of high-speed and low noise information acquisition of ultra-large scale infrared detector, and improves the integration of infrared camera. The test results of the infrared camera show that the infrared camera can simultaneously acquire more than 64 channels of detector signals and the AD conversion rate of per channel is 12 MSPS with the peak data rate of 12.288 Gbps. Circuit noise is less than 0.2 mV (rms) and the system noise is less than 0.6 mV (rms).

Key words: infrared camera, large scale, high integration, low noise, information acquisition

CLC Number:

Shuangxi ZHOU, Lufang LI, Qichao YU, Shengli SUN, Changqing LIN, Yunfei LI. Design of scalable infrared information acquisition architecture based on ASIC and FPGA[J]. Systems Engineering and Electronics, 2025, 47(4): 1057-1066.

Figures/Tables 14

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对比项目	方案
对比项目	传统方案1^[26]	传统方案2^[27]	传统方案3^[15]	传统方案4^[28]	传统方案5^[29]	传统方案6^[10]	本文方案
信号调理电路	分立器件	分立器件	分立器件	分立器件	分立器件	分立器件	ASIC(8通道模拟信号输入)
信息获取电路	2路	2路	12路	4路	16路	4路	中、短波共16个模块, 模拟通道, 64路(主、备份共128路)
峰值数据率/Gbps	—	—	—	—	2.5	—	约13
电路噪声/mV	—	0.13	0.375	0.19	＜0.1	—	0.12

[1]	Shuangxi ZHOU, Lufang LI, Qichao YU, Shengli SUN, Changqing LIN, Yunfei LI. Design of scalable infrared information acquisition architecture based on ASIC and FPGA [J]. Systems Engineering and Electronics, 2025, 47(4): 1057-1066.
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[5]	FENG Zhi-hua1,2,CHEN Xi3,GAO She-sheng1. SystemC system level synthesis method for heterogeneous MPSoC [J]. Journal of Systems Engineering and Electronics, 2010, 32(11): 2484-2488.

Design of scalable infrared information acquisition architecture based on ASIC and FPGA

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