Journal of Systems Engineering and Electronics ›› 2010, Vol. 32 ›› Issue (11): 2484-2488.doi: 10.3969/j.issn.1001-506X.2010.11.48
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SystemC system level synthesis method for heterogeneous MPSoC
Aiming at the shortcoming of the traditional large scale integrated circuit synthesis method, a novel SystemC electronic system level synthesis (SLS) method is proposed. The heterogeneous multiprocessor system on a chip (MPSoC) hardware architecture which is the target for a system level synthesis system and a SLS synthesis flow are described. The SLS method supports a SystemC untimed model as its design entry and adopts the target MPSoC hardware architecture that has a multiprocessor as the controller and algorithmic IPs as computation accelerators. Furthermore, a system level synthesis integrated development environment (IDE) is implemented, and a MPSoC processor is developed with the IDE. Experimental results show that the proposed synthesis method improves the efficiency of software/hardware mixed MPSoC systems effectively and reduces the time put on the market.
- 1． School of Automation, Northwestern Polytechnical Univ., Xi’an 710072, China;
2． Beijing Inst. of Computer Technology and Application, Beijing 100854, China;
3． Dept. of Electronic Engineering, Tsinghua Univ., Beijing 100084, China
