[1] Govindarajan S,Vemuri R.Dynamic bounding of successor force computations in the force directed list scheduling algorithm[C]//Proceedings of IEEE International Conference on Computer Design (ICCD),1997,752-757. [2] Hwang C T,Lee J H,Hsu Y C.A formal approach to the scheduling problem in high level synthesis[J].IEEE Trans.Comput.-Aided Des.lnteg.Circuits Syst,1991,464-475. [3] Paulin P G,Knight J P.Force-directed scheduling for the behavioral synthesis of ASIC' s[J].IEEE Trans.Computer-Aided Design,1989,210-213. [4] Arato P,Mann Z A,Orban A.Time-constrained scheduling of large pipelined datapaths[J].Journal of Systems Architecture,2005,665-668. [5] Potasman R,Lis J,Alexandru,et al.Percolation based synthesis[C]//Annual ACM IEEE Design Automation Conference Proceedings of the 27 th ACM/IEEE conference on Design automation,1991. [6] Hwang C T,Hsu Y C,Lin Y L.Scheduling for functional pipelining and loop winding[C]//DAC,1991,764-769. [7] Chao L F,LaPaugh A,Sha E.Rotation scheduling:a loop pipelining algorithm[C]//In 30th ACM/IEEE Design Automation Conference,1993,566-572. [8] Dhodhi M K,Hielscher F H,Storer R H,et al.Data-path synthesis using a problem-space genetic algorithms[J].IEEE Trans.Comput.-Aided Des.,1995,47-56. [9] Krishnan V,Katkoori S.A genetic algorithm for the design space exploration of datapaths during high-level Synthesis[J].IEEE Trans.on Evolutionary Computation,2006. [10] Kopuri S,Mansouri N.Enhancing scheduling solutions through ant colony optimization[C]//ISCAS '04:International Symposium on Circuits and Systems,2004. [11] Wang Gang,Gong Wenrui,Kastner Ryan.Instruction scheduling using MAX-MIN ant colony optimization[C]//Great Lakes Symposium on Very Large Scale Integration (GLSVLSI),2005. [12] Dorigo M,Maniezzo V,Colorni A.Ant system:optimization by a colony of cooperating agents[J].IEEE Transactions on Systems,Man and Cybernetics,1996,Part-B,26(1):29-41. [13] Ahmad I,Dhodhi M K,All F M.TLS:a tabu search based scheduling algorithm for behavioral synthesis of functional pipelines[J].The Computer Journal,2000,43(2):152-166. [14] Muller J,Fimmel D,Merker R.Optimal loop scheduling with register constraints using flow graphs[C]///2004 International Symposium on Parallel Architectures,Algorithms and Networks (ISPAN'04),2004. |