系统工程与电子技术 ›› 2025, Vol. 47 ›› Issue (2): 376-389.doi: 10.12305/j.issn.1001-506X.2025.02.05
• 电子技术 • 上一篇
李雪健1,2, 陈永强3, 马宏1,2, 刘杨4, 王育欣1,2, 焦义文1,2,*
收稿日期:
2024-01-22
出版日期:
2025-02-25
发布日期:
2025-03-18
通讯作者:
焦义文
作者简介:
李雪健 (2000—), 男, 博士研究生, 主要研究方向为航天测控通信、天线组阵、星地高速数传Xuejian LI1,2, Yongqiang CHEN3, Hong MA1,2, Yang LIU4, Yuxin WANG1,2, Yiwen JIAO1,2,*
Received:
2024-01-22
Online:
2025-02-25
Published:
2025-03-18
Contact:
Yiwen JIAO
摘要:
针对天线组阵设备链路中相位校准(phase calibration,PCAL)信号的高效率真实相位提取这一需求,首先提出一种优化快速傅里叶变换(fast Fourier transform, FFT)分辨率的PCAL信号真实相位提取方法。为进一步提升计算效率,将该方法与深度计算单元(deep computing unit,DCU)并行计算技术相结合,提出PCAL信号真实相位并行提取方法,并设计实现一种基于并行计算的PCAL信号相位实时提取系统。针对上述改进方法及实时系统进行实验验证,大量实验结果表明,优化FFT分辨率的方法相比传统FFT方法可实现约3倍的加速比;在引入并行计算后,加速比进一步提升近一个数量级,基于并行计算的PCAL信号相位实时提取系统可实现对有效带宽为2.2 GHz及以下、信号间隔为1 MHz、量化位数为8 bit的PCAL信号的相位实时提取。此外,设计的实时系统亦适用于其他变频设备的链路标校。
中图分类号:
李雪健, 陈永强, 马宏, 刘杨, 王育欣, 焦义文. 基于并行计算的PCAL信号相位实时提取系统设计[J]. 系统工程与电子技术, 2025, 47(2): 376-389.
Xuejian LI, Yongqiang CHEN, Hong MA, Yang LIU, Yuxin WANG, Yiwen JIAO. Design of PCAL signal phase real-time extraction system based on parallel computing[J]. Systems Engineering and Electronics, 2025, 47(2): 376-389.
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