不完美硬件实现对下行NOMA短包通信的影响

doi:10.12305/j.issn.1001-506X.2025.01.30

Abstract

Abstract:

To achieve ultra-reliability and low-latency communication (URLLC), the impacts of hardware impairment (HI), channel estimation error (CEE) and imperfect successive interference cancellation (SIC) on the performance of downlink two-user non-orthogonal multiple access (NOMA) system with short packet communication (SPC) over Nakagami-m and Rician fading channels are investigated. Firsty, the expressions of average block error rate (BLER) for the users over these two channels are given. Then, under the constraints of users' average BLER, an optimization algorithm, which jointly optimizes the power allocation and the length of pilot sequence, is proposed. Finally, the simulation results verify the accuracy of the analytical results, and show that HI, CEE and imperfect SIC have a great influence on the performance of NOMA SPC system. Moreover, there exists a tradeoff optimization between the power allocation and the length of pilot sequence to accomplish URLLC for NOMA SPC system.

Key words: non-orthogonal multiple access (NOMA), hardware impairment (HI), channel estimation error (CEE), imperfect successive interference cancellation (SIC), short packet communication (SPC)

CLC Number:

TN92

Mingxiu MO, Lei YUAN, Yan LEI, Huahua YUAN. Impact of imperfect hardware implementation on downlink NOMA short packet communication[J]. Systems Engineering and Electronics, 2025, 47(1): 296-306.

Figures/Tables 7

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Impact of imperfect hardware implementation on downlink NOMA short packet communication

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