Abstract:

In some methods of test generation, an analog device under test (DUT) is treated as a discrete time digital system by placing it between a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC). In this way the test patterns and responses can be performed and analyzed in the digital domain. A test generation algorithm based on the support vector machine (SVM) is proposed, and SVM is used for classification. This method uses the test patterns derived from the test generation algorithm as input stimuli, and the samples output responses of the analog DUT are applied for fault detection. In order to reduce the computational cost, this paper uses non-equidistant sampling to compress the impulse-response sample vectors. It ensures the efficiency of test generation when reducing the dimension of the sample space.