高速并行FIR滤波器的FPGA实现

Abstract

Abstract: Based on polyphase decomposition,a novel finite impulse response(FIR) filter structure is proposed,which increases the running speed by L times compared with the serial FIR filter,where L is the number of subfilters,and the parallel FIR filter only introduces very small delay.Firstly the theoretical foundation of parallel FIR filters is analyzed.An example of the floating point parallel 8-channel FIR filter is given to verify the algorithm.Then a fixed point parallel FIR filter is designed,which has optimum canonical signed digits(CSD) coefficients.Each subfilter is also pipelined to increase the running speed.Finally the fixed point parallel FIR filter is implemented in Altera's Stratix II field programmable gate array(FPGA).Compiling and deployment results show that the parallel FIR filters run at the sampling rate up to 2 GHz.

CLC Number:

TN911.7

ZHANG Wei-liang, ZHANG Yu, YANG Zai-chu, YANG Zhi-xing. FPGA implementation of high speed parallel FIR filters[J]. Journal of Systems Engineering and Electronics, 2009, 31(8): 1819-1822.

References

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FPGA implementation of high speed parallel FIR filters

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