Fig.1

Flowchart of CD-SDM"

Fig.2

Block diagram of working reserve system reliability"

Fig.3

Single circuit solution"

Fig.4

Stress-level diagram of reliability enhancement test"

Fig.5

Stress-level diagram of estimated values of working limit and failure limit"

Fig.6

Temperature stepping enhanced test profile design framework"

Table 1

Derating levels of different applications"

Fig.7

Structural size of a certain missile electronic product"

Table 2

Power consumption of main components  W"

Table 3

Rated temperature of main components  ℃"

Fig.8

Product reliability block diagram"

Table 4

Main material properties"

Fig.9

Simulation temperature boundary conditions"

Table 5

High and low temperature test chamber model and parameter indicators"

Table 6

Thermal resistance model and parameter indicators"

Table 7

Temperature recorder model and parameter indicators"

Fig.10

Temperature test and thermocouple fixed position for low temperature stepping and mapping test"

Fig.11

Simulation temperature changing curves"

Table 8

Stability time and temperature of simulation temperature test points at -50~-40 ℃"

Fig.12

Cross-sectional temperature distribution of a certain missile electronic equipment"

Table 9

Temperature of main components at 22 ℃  ℃"

Fig.13

Component with maximum temperature hysteresis coefficient"

Fig.14

Temperature curve of traditional methods"

Table 10

Thermal stabilization time of traditional methods"

Fig.15

Temperature changing curve by equipartition method"

Table 11

Thermal stabilization time of equipartition method"

Fig.16

Temperature changing curve divided in steps of the CD-SDM"

Table 12

Thermal stabilization time divided in steps of the CD-SDM"

Table 13

Comparison of three methods"

Fig.17

Thermal stability curves of three methods"

Fig.18

Output signal when the product is normal"

Fig.19

Output signal when the product is abnormal"

Table 14

Test temperature and test results"