Journal of Systems Engineering and Electronics ›› 2011, Vol. 33 ›› Issue (4): 769-773.doi: 10.3969/j.issn.1001-506X.2011.04.12

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Design and implementation of space borne SAR IF digital receiver on FPGA

HUANG Jie-wen1,2, QI Hai-ming1, LI Zao-she1, YU Wei-dong1   

  1. 1. Institute of Electronics, Chinese Academy of Sciences, Beijing 100080, China;
    2. Graduate University of the Chinese Academy of Sciences, Beijing 100049, China
  • Online:2011-04-25 Published:2010-01-03

Abstract:

The design and implementation of a space borne synthetic aperture radar (SAR) inter frequency (IF) digital receiver including data formation on field programmable gate arrays (FPGA) is proposed. An improved polyphase frequency down converting structure of different bandwidth signals is implemented, considering the limited multipliers in FPGA and after carefully analyzing the relationships among IF, sampling frequency and decimation factor. To alleviate data downlink pressure, a block adaptive quantization (BAQ) module with a flexible compression ratio is developed. Finally the design instance is given and the properties are verified by experimental results. 2‰ mainlobe expansion and a 93% integral sidelobe ratio of theoretical value after matching filter are achieved with 8:3 BAQ compression ratio, 14.6 dB I/Q channel signal to noise ratio (SNR).

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