基于HLS的高精度位移测量算法的硬件加速设计

doi:10.12305/j.issn.1001-506X.2025.02.01

Abstract

Abstract:

To address the requirements of high-precision displacement sensors for high-speed displacement measurement algorithms for operating speed, protability and lower researching and developing cost, a hardware acceleration design method for high-precision measurement algorithms based on high-level synthesis (HLS) technology is proposed. By using HLS, the C++code is synthesized into Verilog. The design strategy for high-precision displacement measurement algorithms employs optimization techniques such as pipelining and array partitioning in HLS to achieve hardware acceleration and the design is packaged as an intellectual property (IP) core to enhance portability of the proposed algorithm. The measurement system is implemented on a Xilinx Kintex-7 field-programmable gate array (FPGA) XC7K325TFFG676 chip as a carrier, and experimental results demonstrate that the entire operating time of the proposed algorithm is 91.8 μs, which is 308.2 μs shorter than the implementation time of a digital signal processor (DSP), with the measurement accuracy of 44.44 nm, stability of 49.20 nm, and linearity of 0.503‰.

Key words: high-level synthesis (HLS) technology, displacement measurement, field-programmable gate array (FPGA), hardware acceleration

CLC Number:

TP33

Haoran CHEN, Tianhao WANG, Meina LU, Maoxin SONG, Huan LUO, Xiaoyu WU, Donggen LUO, Zhenwei QIU. High-precision displacement measurement algorithm based on HLS for hardware acceleration design[J]. Systems Engineering and Electronics, 2025, 47(2): 341-351.

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性能	优化前		优化后
性能	最小	最大	最小	最大
时延	8 485	32 294	4 118	27 927
间隔	8 485	32 294	4 118	27 927

优化状态	资源名称
优化状态	BRAM	DSP	FF	LUT
优化前	12	27	9 756	16 711
优化后	10	27	8 927	16 233

性能	优化前		优化后
性能	最小	最大	最小	最大
时延	4 118	27 927	872	5 540
间隔	4 118	27 927	872	5 540

优化状态	BRAM	DSP	FF	LUT
优化前	10	27	8 927	16 233
优化后	10	49	13 761	21 273

性能	优化前		优化后
性能	最小	最大	最小	最大
时延	872	5 540	858	5 520
间隔	872	5 540	858	5 520

High-precision displacement measurement algorithm based on HLS for hardware acceleration design

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最优化	BRAM	DSP	FF	LUT
优化前	6	49	46 909	180 172
优化后	8	49	27 552	117 682

时间	均值/mm	3倍标准差/nm	峰谷值/mm
30 s	24.23	44.44	0.178 5
30 min	24.25	49.20	0.276 7

实验	方案	工作频率/MHz	处理时间/μs
实验1	FPGA	100	91.8
实验2	DSP	1 000	400

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